Definition

A simple makefile consists of rules with the following shape
target … : dependencies …
command
 …

 …
A target is the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action such as clean, install, configure.
A dependency is a file that is used as input to create the target. A target depends on several files.
A command is an action that make carries out. A rule may have more than one command, each on its own line. Note: you have to put a tab character at the beginning of every command line! If you try to put spaces instead of tab,
make will not work at all. Make sure to tab.

Usually a command is in a rule with dependencies and serves to create a target file if any of the dependencies change. However, the rule that specifies commands for the target need not have dependencies. For example, the rule containing the delete command associated with the target `clean’ does not have dependencies.
A rule, then, explains how and when to remake certain files which are the targets of the particular rule. make carries out the commands on the dependencies to create or update the target. A rule can also explain how and when to carry out an action.
A makefile may contain other text besides rules, but a simple makefile need only contain rules.

A simple makefile

edit: main.o test.o junk.o
gcc -o edit main.o test.o junk.o
main.o: main.c main.h
gcc -c main.c
test.o: test.c test.h
gcc -c test.c
junk.o: junk.c junk.h test.h
gcc -c junk.c
clean:
rm -rf *.o
rm -rf core

After you run make command, it will create an executable edit if a successful compilation. to run the program just type ./edit. To delete the object files you can use the clean method. just type make clean. Here, * is a regular expression that matches any characters followed by . and o. See the see the regular expression section for mored etail about regular expression.
Makefile with variables

In our example, we had to list all the object files twice in the rule for `edit’  (repeated here):
edit : main.o test.o junk.o
gcc -o edit main.o test.o junk.o

Such duplication is error-prone; if a new object file isa dded to the system, we might add it to one list and forget the other. We can eliminate the risk and simplify the makefile by using a variable. Variables allow a text string to be defined once and substituted in multiple places later.
Common variable names for objects:

OBJECTS, objs, OBJS, obj, or OBJ which is a list of all object file names. We would define such a variable objects with a line like this in the makefile:
objects = main.o test.o junk.o
Then, each place we want to put a list of the object file names, we can substitute the variable’s value by writing `$(objects)\’.
Here is how the complete simple makefile looks when you use a variable for the object files:
objects = main.o test.o junk.o
edit : $(objects)
gcc -o edit $(objects)
main.o : main.c main.h
gcc -c main.c
test.o: test.c test.h
gcc -c test.c
junk.o: junk.c test.h junk.h<br>
gcc -c junk.c
clean :
rm -rf $(objects)

Another example

If you have more than one compiler such as gcc, cc, g and want to chage the compiler, all you need to do is modify the first line below. change gcc to cc to change the compiler from gcc to cc.
Compiler = gcc
objects = main.o test.o junk.o

edit : $(objects)
$(Compiler) -o edit $(objects)
main.o : main.c main.h
$(Compiler) -c main.c
test.o: test.c test.h
$(Compiler) -c test.c
junk.o: junk.c test.h junk.h
$(Compiler) -c junk.c
clean :
rm -rf $(objects)<br>